1. Field of the Invention
The invention relates to the field of return buffers. In particular, the invention relates to using and maintaining a return buffer in an instruction pipeline of a microprocessor.
2. Description of Related Art
Microprocessors have instruction pipelines in order to increase program execution speeds. However, when there is a branch instruction, the pipeline may stall while waiting for the branch condition to resolve before fetching the next instruction, since it is not known whether the branch will be taken. In order to prevent stalls in the pipeline while waiting for the next instruction to be fetched, microprocessors employ branch prediction circuitry to predict whether a branch will be taken. Certain types of branch instructions are associated with program calls to subroutines. A typical program calls a subroutine by issuing a call instruction, citing the address of the subroutine to which the program should branch. The subroutine typically ends with a return instruction, which causes a branch back to the program that issued the call. When the call instruction is executed, the address of the next sequential instruction is pushed onto a branch prediction buffer called a return buffer. When the return instruction is retired, the return buffer is popped, thereby providing the appropriate return address.
In a microprocessor that has multiple instruction sources, such as instruction fetch, instruction decode, and branch prediction, multiple pointers from each instruction source to the return buffer are maintained and the return address is sent from the return buffer to the appropriate instruction source when needed. However, there is the problem of latency for instruction sources or pipeline units that are not located close to the return buffer. Sources or units not located close to the return buffer may take a long time to obtain a correct return address from the return buffer, thus requiring a stall in the pipeline to wait for the return address.